library verilog;
use verilog.vl_types.all;
entity lab6_vlg_check_tst is
    port(
        key_col         : in     vl_logic_vector(3 downto 0);
        overflow        : in     vl_logic;
        seg             : in     vl_logic_vector(7 downto 0);
        sel             : in     vl_logic_vector(2 downto 0);
        sampler_rx      : in     vl_logic
    );
end lab6_vlg_check_tst;
